In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of\nthe partial products and parallel binary operations based on 2-digit columns. 1 Ã?â?? 1-digit multipliers used for the partial product\ngeneration are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 Ã?â?? 1-digit\nmultiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products.Abinarydecimal\ncompressor structure is developed and used for partial product reduction. These reduced partial products are added in\noptimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance\nand reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on\nthe critical path delay reduction. Pipelined BCD multipliers were implemented for 4 Ã?â?? 4, 8 Ã?â?? 8, and 16 Ã?â?? 16-digit multipliers. Our\nrealizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.
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